In the field of semiconductor memory devices such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM), it is known to employ capacitors containing noble metals such as Pt, Pd, Ir, and Ru as one of the electrodes and high-.epsilon. or ferroelectric materials as the dielectric. These materials provide a high-dielectric constant capacitor suitable for use in Gigabit memory applications.
Despite their importance in providing Gigabit memory devices, noble metals and high-.epsilon. or ferroelectric dielectrics have some problems associated therewith. Insofar as the noble metals are concerned, Pt, along with the other noble metals are difficult to pattern by conventional techniques such as reactive-ion etching (RIE) or wet chemical etching, especially at the deep sub-micron dimensions required for high density DRAM and FRAME. Alternative patterning Techniques using electrochemical deposition processes such as through-mask plating have been described in U.S. Pat. No. 5,789,320.
Recently, it has been reported that 10 nm Ta.sub.2 O.sub.5 films deposited on Pt electrodes could be produced with an oxide equivalent thickness of 0.9 nm and a leakage current density of less than 10 nA/cm.sup.2 (sufficient to meet the requirements of future DRAMs), See, for example, "Structure and Electrical Properties of thin Ta.sub.2 O.sub.5 Deposited on Metal Electrodes, K. Kishiro, et al., Jap. J. Appl. Phys. 1, 37, 1336 (1998). However, in order to use Ta.sub.2 O.sub.5 and other high-e dielectrics or ferroelectric materials successfully in future memory devices, bottom electrode structures will need to have surface area of 1 sq. micron or greater in a very much smaller footprint. Without such enhanced-area electrodes, high density devices with the desired capacitance will require :dielectrics such as (Ba,Sr)TiO.sub.3 (BST) which have lower oxide equivalent thicknesses, but are more challenging to integrate than Ta.sub.2 O.sub.5.